In the manufacture of integrated circuits, interconnects are generally formed on a semiconductor substrate using a copper dual damascene process. Such a process typically begins with a trench and via being etched into a dielectric layer and then filled with a barrier/adhesion layer and a seed layer using a physical vapor deposition (PVD) sputtering process. An electroplating process is then used to fill the via and trench with copper metal to form the interconnect. However, as device dimensions scale down and the features become narrower, the aspect ratio of the features becomes more aggressive. The line-of-sight PVD process gives rise to issues such as trench overhang of the barrier/adhesion, and seed layers, leading to pinched-off trench and via openings during plating, and inadequate gap fill.